1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a memory area and a logic circuit area. More specifically the invention pertains to a method of manufacturing a semiconductor device, on which each of non-volatile memory devices formed in the memory area has two charge accumulation regions relative to one word gate.
2. Description of the Related Art
One type of non-volatile semiconductor memory devices is MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon), in which a gate insulating layer between a channel area and a control gate is a multi-layered body of a silicon oxide layer and a silicon nitride layer and charges are trapped by the nitride silicon layer.
FIG. 24 shows a known MONOS non-volatile semiconductor memory device (refer to: Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-123).
Each MONOS memory cell 100 has a word gate 14, which is formed on a semiconductor substrate 10 via a first gate insulating layer 12. A first control gate 20 and a second control gate 30 are formed as side walls on both sides of the word gate 14. A second gate insulating layer 22 is present between the bottom of the first control gate 20 and the semiconductor substrate 10. An insulating layer 24 is present between the side face of the first control gate 20 and the word gate 14. Similarly the second gate insulating layer 22 is present between the bottom of the second control gate 30 and the semiconductor substrate 10. The insulating layer. 24 is present between the side face of the second control gate 30 and the word gate 14. Impurity layers 16 and 18, each of which constitutes either a source area or a drain area, are formed in the semiconductor substrate 10 to be located between the control gate 20 and the control gate 30 of adjoining memory cells.
Each memory cell 100 accordingly has two MONOS memory elements on the side faces of the word gate 14. These two MONOS memory elements are controlled independently. Namely each memory cell 100 is capable of storing 2-bit information.
A memory area including such MONOS memory cells and a logic circuit area including peripheral circuits of memories are formed on an identical semiconductor substrate in a semiconductor device. A prior art method of manufacturing such a semiconductor device first forms memory cells in the memory area and subsequently forms peripheral circuits in the logic circuit area. The manufacturing method forms diverse wiring layers via an insulating layer, after formation of the memory area and the logic circuit area.
The manufacturing method forms an insulating layer of, for example, silicon oxide, and polishes the insulating layer by CMP (chemical mechanical polishing) technique.
It is desirable that the upper face of the insulating layer after the polishing process is sufficiently flat and even, in order to carry out subsequent processes with high accuracy, for example, in order to form a wiring layer above the insulating layer with high accuracy. The polishing rate of the insulating layer is, however, not constant but is varied. The insulating layer in the logic circuit area is often polished relatively faster than the insulating layer in the memory area. This may cause unevenness on the upper face of the polished insulating layer.
The object of the present invention is thus to provide a technique of making surface of an insulating layer sufficiently flat and even after a polishing process in a manufacturing method of a semiconductor device including a memory area and a logic circuit area.
In order to attain at least part of the above and the other related objects, the present invention is directed to a first method of manufacturing a semiconductor device, which includes a memory area having a non-volatile memory device and a logic circuit area having a peripheral circuit of the non-volatile memory device. The first manufacturing method includes the steps of: forming an element separating region on surface of a semiconductor layer to attain insulation between semiconductor elements; forming a first insulating layer above the semiconductor layer; forming a first conductive layer above the first insulating layer; forming a stopper layer above the first conductive layer; and patterning the stopper layer and the first conductive layer in the memory area, while patterning the stopper layer and the first conductive layer in the logic circuit area to create a dummy gate layer on the element separating region in the logic circuit area. The first manufacturing method further includes the steps of: forming an ONO membrane over whole surface of the memory area and the logic circuit area; forming a second conductive layer above the ONO membrane; carrying out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area; patterning the first conductive layer in the logic circuit area other than the element separating region to create a gate electrode of an insulated gate field effect transistor in the logic circuit area; forming a second insulating layer over whole surface of the memory area and the logic circuit area; and polishing the second insulating layer to make the stopper layer in the memory area exposed.
The first manufacturing method of the invention patterns the stopper layer and the first conductive layer in the logic circuit area to create the dummy gate electrodes above the element separating region in the logic circuit area and thereby makes the formation density of the gate electrodes and the dummy gate electrodes in the logic circuit area approximate to the formation density of the first conductive layers in the memory area. The density of occurrence of irregularities on the surface of the insulating layer in the logic circuit area thus approaches to the density of occurrence of irregularities on the surface of the insulating layer in the memory area. There is accordingly a less difference in height of the surface of the insulating layer between the memory area and the logic circuit area. This arrangement effectively reduces the unevenness on the surface of the insulating layer, which may arise in the process of polishing the insulating layer, and makes the polished insulating layer sufficiently flat and even.
The present invention is also directed to a second method of manufacturing a semiconductor device, which includes a memory area having a non-volatile memory device and a logic circuit area having a peripheral circuit of the non-volatile memory device. The second manufacturing method includes the steps of: forming an element separating region on surface of a semiconductor layer to attain insulation between semiconductor elements; forming a first insulating layer above the semiconductor layer; forming a first conductive layer above the first insulating layer; forming a stopper layer above the first conductive layer; and patterning the stopper layer and the first conductive layer in the memory area, while patterning the stopper layer and the first conductive layer in the logic circuit area to create a dummy gate layer on the element separating region in the logic circuit area. The second manufacturing method also includes the steps of: forming an ONO membrane over whole surface of the memory area and the logic circuit area; forming a second conductive layer above the ONO membrane; carrying out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area; removing the stopper layer in the logic circuit area; patterning the first conductive layer in the logic circuit area to create a gate electrode of an insulated gate field effect transistor in the logic circuit area; and forming side wall insulating layers on both side faces of at least the gate electrode. The second manufacturing method further includes the steps of: forming a first impurity layer as either one of a source area and a drain area of the non-volatile memory device and a second impurity layer as either one of a source area and a drain area of the insulated gate field effect transistor; forming a silicide layer on surface of the first impurity layer, the second impurity layer, and the gate electrode; forming a second insulating layer over whole surface of the memory area and the logic circuit area; polishing the second insulating layer to make the stopper layer in the memory area exposed; removing the stopper layer in the memory area; and patterning the first conductive layer in the memory area, so as to create a word gate of the non-volatile memory device in the memory area.
Like the first manufacturing method, the second manufacturing method of the invention effectively reduces the unevenness on the surface of the second insulating layer, which may arise in the process of polishing the second insulating layer, and makes the surface of the polished second insulating layer sufficiently flat and even.